FIGS. 2(a) to 2(d) are cross-sectional views showing process steps for producing a prior art semiconductor device. In FIG. 2, reference numeral 1 designates a semi-insulating GaAs substrate. An undoped GaAs layer 2 of about 5000 angstroms thickness is disposed on the substrate 1. A two dimensional electron gas 3 is disposed at an upper portion of the undoped GaAs layer 2. by an n type AlGaAs layer 4 having a film thickness of about 1000 angstroms and impurity concentration of about 3.times.10.sup.17 cm.sup.-3 disposed on the undoped GaAs layer 2. An n type GaAs layer 5 of about 2000 angstroms thickness and impurity concentration of about 3.times.10.sup.18 cm.sup.-3 is disposed on the n type AlGaAs layer 4. A source electrode 6 and a drain electrode 7 are disposed on the n type GaAs layer 5. Reference numeral 8 designates a drain electrode photoresist pattern and reference numeral 9 designates a gate electrode.
The device will operate as follows.
Electrons are supplied from the n type AlGaAs layer 4 to the undoped GaAs layer 2 and a two dimensional electron gas 3 is generated in the undoped GaAs layer 2. The movement of the electrons in the two-dimensional electron gas 3 is controlled by the gate electrode 9, and the current flowing between the drain electrode 6 and the source electrode 7 is thus controlled. Since the electrons in the two-dimensional electron gas 3 move in the undoped GaAs layer 2, they are not scattered by impurities. Therefore, an FET of quite low noise characteristics is obtained.
The production method will be described.
The structure shown in FIG. 2(a) is produced by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). Next, a source and a drain electrode 6 and 7 are produced thereon by vapor deposition and using the liftoff method. Then, a gate electrode photoresist pattern 8 is produced, and a recess is formed at the n type GaAs substrate 5 by wet etching using a sulfuric acid or tartaric acid etchant and photoresist pattern 8 as a mask. A gate electrode 9 is deposited at the recess by vapor deposition and the lift-off method, thereby completing a device.
Generally in a HEMT or MESFET semiconductor device, a narrow gate length is required for the enhancement of performance such as characteristics speed. In the prior art semiconductor device constructed in such a manner, however, the gate length is restricted by the size of the photoresist pattern, and it is difficult to miniaturize the gate. Furthermore, the increase in the gate resistance accompanying a narrow gate width has caused a problem.
Furthermore, in the HEMT or MESFET semiconductor device, parasitic capacitance and parasitic resistance must be reduced to enhance element performance. It is especially, important to suppress the series resistance between the source and gate electrode. In the above-described prior art semiconductor device, however, since the gate electrode and the source/drain electrode are located far from each other, in order to reduce the source to gate series resistance, formation of etching a recess by the n type GaAs layer is required. Etching the recess has caused problems in the uniformity and reproducibility in the current value and the pinch-off voltage.
FIG. 3 shows another prior art GaAs MESFET disclosed in Japanese Published Patent Application 63-36577. In this GaAs MESFET, indium ions 40 are ion implanted into a GaAs semi-insulating substrate 41 on which an active layer 42 is deposited. Annealing is carried out to produce an In.sub.x Ga.sub.1-x As layer 43 whose energy band gap is gradually lower as is closer to the surface. Thereafter, a metal layer is produced thereon, thereby producing source/drain electrodes 44 providing ohmic contacts on the n.sup.+ type InGaAs layers 43 without alloying.
In this prior art device, however, fine patterning of the gate is not attempted, and the gate electrode and the source/drain electrode are located far from each other, therefore, the source series resistance cannot be reduced.
FIG. 4 shows still another prior art GaAs MESFET disclosed in Japanese Published Patent Application 60-50967. In this GaAs MESFET, an n.sup.+ type Ge thin layer 51 having the same function as the above-described n.sup.+ type InGaAs layer, that is, providing non-alloying ohmic contact source/drain electrodes, is disponsed on an active layer 52. The Ge layer 51 is selectively etched (over-etched in the transverse direction) from the gate aperture portion of the insulating film for space 53 which is disposed on the Ge layer 51 and a gate 54 is disposed on the exposed surface of the etched portion. Further, the insulating film for spacer 53 is formed by photolithography at both sides of the gate aperture, and source and drain electrodes 55 and 56 are produced thereon. Thus, the effective interval between the source and gate can be controlled, and further, the source, gate, and drain electrodes can be produced from the same material at the same time, thereby simplifying the production process.
In this prior art method, however, the fine patterning of the gate cannot be conducted without increasing the gate resistance. Furthermore, since the production of the source/drain electrodes is independently conducted by photolithography after the production of the gate aperture, the production of the source/drain electrodes is not self-aligning with the gate electrode, also producing an insufficient reduction of the source series resistance.